Field of Invention
The present invention relates to the field of liquid crystal display, and more particularly to a GOA circuit and a liquid crystal display device.
Description of Prior Art
Liquid crystal displays (LCDs) such as flat panel display devices are widely used in mobile phones, televisions, personal digital assistants, digital cameras, notebooks, desktop, other consumer electronics products and etc. for high quality, power saving, thin body and wide application range. The LCDs has become the mainstream in display device.
In the active LCD, each sub-pixel has a thin film transistor (TFT) whose gate electrode is connected with a horizontal scanning line, a drain electrode is connected with a data line in the vertical direction, and a source electrode is connected with a pixel electrode. Applying a sufficient voltage on the horizontal scanning line, all the TFTs on the horizontal scanning line are opened, where the pixel electrodes on the horizontal scanning line will be conducted with the data lines in the vertical direction, the display-signal voltage on the data line is written onto the pixels, to control the transparency of different liquid crystal for achieving the effect of color control. At present, the driving of the horizontal scanning line of the active LCD panel is mainly realized by an external chip (IC) of the panel. The external IC can control the charging and discharging of each stage horizontal scanning line from stage to stage. Gate on Array, GOA technology, the gate driver on array technology, which use the conventional process of the LCD panel to produce the row scanning driving circuit of gate electrodes on the substrate so that it can complete the row-by-row scanning to the gate electrodes.
The conventional GOA circuits typically include cascaded multiple GOA units, each stage GOA unit corresponds to drive a horizontal scanning line. The main structure of the GOA unit includes a pull-high circuit, a pull-high control circuit, a pull-down circuit, a pull-down sustain circuit, and a boast capacitor for the potential elevation. The pull-high control circuit can be called as a pre-charging circuit. The pull-high circuit is mainly responsible for outputting the clock signal as a gate signal. The pull-high control circuit is responsible for controlling the opening time of the pull-high circuit. Generally, the pull-high control circuit is connected with a previous stage GOA circuit to receive a stage-transfer signal or the gate signal. The pull-down circuit is responsible for pulling the gate signal low to a low potential at the first moment, that is, the gate signal is turned off. The pull-down sustain circuit is responsible for maintaining the gate output signal and the gate signal of the pull-high circuit (commonly referred to as Q point) in a closed state (i.e., negative potential). The boast capacitor is responsible for a second potential elevation of the Q point, which is beneficial to the output G(N) of the pull-high circuit.
Because GOA technology can save the gate chip (gate IC), to achieve a narrow border and other advantages, the current GOA technology has been widely used in panel design, so that the design of the new GOA circuit is necessary. However, in the case where the start signal STV is currently used as the GOA ON signal and the Q-point pre-charging signal, the waveforms of the waveforms of the Q point belong to the on the first list of stages may be inconsistent due to the difference in the pre-charging time.
Please refer to FIG. 1, the conventional GOA circuit structure is shown, the GOA circuit structure is mainly constituted by the pull-high control circuit T11, the pull-high circuit (including T21, T22), the pull-down circuit, the pull-down sustain circuit, and a boast capacitor Cb and so on. To the N-th stage GOA unit, the pull-high control unit is connected with a stage-transfer signal output terminal ST(N−4) and a gate signal output terminal G (N−4) of a (N−4)th stage GOA unit and responsible for controlling the opening time of the pull-up circuit and pre-charging the node Q (N). The pull-high unit is connected with a clock signal CK and a stage-transfer signal output terminal ST(N) of the (N)th stage GOA unit, and is responsible for outputting the clock signal CK to corresponding horizontal scanning lines through a gate signal output terminal G(N) of the N-th stage and outputting the stage-transfer signal of the N-th stage GOA unit. The pull-down unit is responsible for pulling down the gate signal output terminal G(N) of the N-th stage. The pull-down sustain unit may be used to keep to pull down the voltage of the gate signal output terminal G(N) and the voltage of the node Q (N) of the pull-high unit, so that the gate signal outputted from the gate signal output terminal G (N) is maintained in the OFF state.
Please refer to FIGS. 2 and 3; FIG. 2 is an illustrative diagram of the output signal of the node Q of the GOA circuit structure according to the conventional art, the horizontal axis for the time, the vertical axis for the voltage. It shows the waveforms of 1st to 8th stage GOA units. FIG. 3 is an illustrative diagram of the input signal of the CK and the input signal of the STV of the GOA circuit structure according to the conventional art, the horizontal axis for the time, and the vertical axis for the voltage. It shows the start signal STV and the high-frequency clock signal CK inputted to 1-6 stage GOA units, it can be seen in FIG. 3 that the high-frequency clock signal CK of all stage of GOA units are the normal CK output waveform, CK waveform are generated order-by-order, there is no relative advance output. Since the pull-up control circuit needs to input the stage-level signal and the gate signal of the (N−4)th stage GOA unit, the preceding stages of the GOA circuit needs to be inputted with the start signal STV instead of the stage-transfer signal as the ON signal of the GOA and the pre-charging signal of the node Q, resulting that the output waveforms of the first three nodes Q are not consistent with a normal level node Q(see FIG. 2).